This invention relates to memory systems which store digital data and use logic gate arrays to correct errors in the data; and more particularly, it relates to systems of the above type which operate on a low DC (direct current) power.
In the prior art, perhaps the most widely used memory systems are those which employ dynamic RAM (DRAM) chips. Several million of these DRAM Chips are sold each year. Presently, a single DRAM chip is capable of storing 256,000 bits of information; whereas ten years ago, a single DRAM chip could store only about 1,000 bits.
To a large extent, this increase in the number of bits in a single DRAM chip has been achieved by shrinking the geometries of the various circuit patterns which make up the chip and thereby reduce the size of each memory cell. However, as the size of the DRAM memory cell decreases, that cell becomes more susceptible to "soft" errors.
Soft errors are of a transient nature and occur randomly within the chip. Alpha particles, as emitted by trace amounts of impurities which exist within the chip itself, are a common source of soft errors. Once emitted, the alpha particles generate electron hole pairs; and they alter the charge that is stored in a cell as information. As the cell becomes smaller, the amount of charge alteration that can occur without producing an error decreases.
Accordingly, in an effort to avoid the soft error problem, memory systems employ error-correcting codes. With such systems, an error code is written into the DRAM chips along with the data. This error code is generated such that it allows errors which occur in the data during storage to be corrected when the data is read from the memory. Hamming codes are a common example of these error-correcting codes; and they are described at pages 126-128 in a book entitled Computer Networks by Andrew Tanenbau, 1981, Prentice-Hall, Inc. Other codes are also described in this book.
A problem however, with error-correcting codes is that the required number of check bits increases with the number of data bits per data word and with the number of errors which are to be corrected per data work. For example, page 127 of the above book gives the formula m+r+1&lt;2.sup.r which must be met for Hamming codes that correct single bit errrors, wherein m is the number of data bits per word, and r is the number of check bits per word.
If the stored data word is one hundred eighteen bits and two errors are to be corrected via Hamming codes in that data word, then seventeen check bits are needed per data word. These check bits have 2.sup.17 or 131,072 different binary combinations; and these binary combinations must be decoded when an error occurs to determine which bits in the data word need to be corrected. Such decoding requires a huge amount of logic which in turn dissipates a proportionate amount of power. Thus a problem exists of how to design this circuitry such that its power dissipation is reduced to the point where the system can be integrated on a small number of semiconductor chips without exceeding each chip's maximum power dissipation.
Accordingly, a primary object of the invention is to provide a memory system in which the above described power dissipation problem is substantially reduced.